The present invention relates to a semiconductor integrated circuit in which a circuit for testing an LSI is incorporated.
Boundary-scan architecture has been disclosed by IEEE Std 1149.1a-1993, pp. A8-A12, JP-A-4-105077, JP-A-4-20879 and JP-A-7-151829.
The boundary scan is a system for testing the mounting condition (or the short-circuiting and disconnection) of wiring of an LSI mounted on a board or package. In order to realize this testing, a boundary scan circuit connected to a signal input/output pin of the LSI is incorporated in the LSI.
The boundary scan circuit for testing has the following problem. Namely, notwithstanding that the boundary scan circuit does not contribute to the essential specification of the LSI, the circuit occupies a large area of the LSI chip and hence a so-called overhead becomes large. Therefore, a chip portion capable of being used for the realization of the essential operation specification is oppressed or the area of the chip is increased.